VxWorks CPCI Fiber Communication Card Design and Driver Development
High-speed and reliable communication is critical in modern platform inertial navigation systems. Traditional RS422 serial interfaces often become bottlenecks due to limited bandwidth and susceptibility to electromagnetic interference. To address these limitations, this article presents the design and implementation of a 6U CPCI fiber optic communication card based on the PCI9030 bridge chip and the VxWorks real-time operating system.
The solution combines a high-speed optical transmission channel, DSP-based protocol processing, dual-port RAM communication, and a deterministic VxWorks device driver architecture. The result is a robust embedded communication platform suitable for aerospace, industrial, and mission-critical navigation systems.
๐ Introduction #
Inertial navigation platforms require deterministic, low-latency, and noise-resistant communication between the navigation computer and the inertial stabilization subsystem. Conventional electrical serial interfaces such as RS422 provide simplicity but suffer from:
- Limited communication throughput
- Susceptibility to electromagnetic interference (EMI)
- Reduced scalability for modern sensor fusion systems
- Higher latency under heavy data exchange
To overcome these issues, a fiber optic communication architecture was introduced using a CompactPCI (CPCI) platform combined with the VxWorks hard real-time operating system.
Why CPCI and VxWorks? #
CPCI Advantages #
CompactPCI provides:
- Rugged Eurocard mechanical structure
- Hot-swappable industrial design
- High PCI bus bandwidth
- Excellent vibration resistance
- Long lifecycle support for military and industrial applications
VxWorks Advantages #
VxWorks provides:
- Deterministic scheduling
- Low interrupt latency
- Fast context switching
- Mature PCI and driver frameworks
- Strong support for embedded multi-tasking systems
The combination makes the platform ideal for high-reliability embedded communication systems.
๐งฉ Overall Hardware Architecture #
The communication card is implemented as a 6U CPCI extension board. The overall architecture consists of several tightly integrated subsystems.
Core Components #
| Component | Function |
|---|---|
| PCI9030 | PCI-to-local bus bridge |
| TMS320F2812 DSP | Protocol processing and control |
| CY7B923 / CY7B933 | Optical serializer/deserializer |
| Dual-Port RAM | Shared memory communication |
| CPLD | Timing and bus control logic |
| FIFO Buffers | Data buffering for optical transfer |
The architecture separates host-side PCI communication from DSP-side real-time optical processing, significantly simplifying system integration.
๐ PCI9030 Bridge Design #
The PLX PCI9030 acts as the bridge between the CPCI bus and the local embedded subsystem.
Key PCI9030 Features #
- PCI 2.2 compliant
- Local bus interface
- DMA engine
- Interrupt support
- EEPROM-based configuration
- Memory-mapped local address spaces
PCI Configuration Space #
The EEPROM stores all PCI configuration information, including:
- Vendor ID
- Device ID
- Class Code
- Interrupt routing
- BAR address mapping
- Local bus timing parameters
Local Space Mapping #
The design uses Local Space 0:
| Parameter | Value |
|---|---|
| Address Space | 64 KB |
| Bus Width | 16-bit |
| Base Address | 0x00200000 |
| Descriptor | 0x00400022 |
This allows transparent host access to local bus peripherals and shared memory.
๐ Fiber Optic Communication Channel #
The optical communication subsystem operates at 155 Mbps using 8B/10B encoding compliant with ANSI X3.230.
Optical Components #
| Device | Function |
|---|---|
| CY7B923 | Parallel-to-serial transmitter |
| CY7B933 | Serial-to-parallel receiver |
| Optical Transceiver | Fiber interface |
| FIFO | Buffering and clock decoupling |
Transmission Workflow #
Send Path #
- DSP writes packet into FIFO
- DSP asserts
ENA - CY7B923 generates FIFO read pulses
- Data is encoded using 8B/10B
- Serialized data transmitted optically
When no payload exists, synchronization idle characters are automatically inserted.
Receive Path #
- Optical stream enters CY7B933
- Data is decoded and written into FIFO
- FIFO “not empty” signal triggers DSP interrupt
- DSP ISR reads received data
This architecture minimizes CPU overhead while maintaining deterministic throughput.
๐ง DSP and Dual-Port RAM Communication #
The TMS320F2812 DSP handles:
- Communication protocol processing
- Packet parsing
- Interrupt management
- Peripheral coordination
- Fiber channel control
Dual-Port RAM Mechanism #
Dual-port RAM enables low-latency communication between:
- CPCI host CPU
- DSP local subsystem
Mailbox registers provide interrupt signaling:
| Address | Direction |
|---|---|
0x1FFE |
Host โ DSP |
0x1FFF |
DSP โ Host |
This mechanism avoids expensive polling and enables efficient asynchronous communication.
โ๏ธ CPLD Logic Design #
A CPLD generates all major timing and control signals, including:
- FIFO control
- Address decoding
- Interrupt routing
- Local bus arbitration
- DSP handshake logic
Benefits include:
- Reduced glue logic
- Deterministic timing
- Simplified PCB routing
- Easier future upgrades
๐ฅ VxWorks Device Driver Architecture #
The driver follows the standard VxWorks I/O system model.
Driver Responsibilities #
- PCI device discovery
- Memory mapping
- Interrupt handling
- DMA/local bus access
- Synchronization
- Device abstraction
Main Driver Components #
| Function | Purpose |
|---|---|
pci9030init() |
PCI device initialization |
pci9030drv() |
Install driver into VxWorks I/O system |
pci9030create() |
Create device node |
pci9030open() |
Open device |
pci9030close() |
Close device |
pci9030read() |
Read local memory |
pci9030write() |
Write local memory |
pci9030ioctl() |
Device control operations |
pci9030isr() |
Interrupt service routine |
pci9030inthandle() |
Deferred interrupt processing task |
๐ Interrupt Handling Design #
The driver uses the standard ISR + semaphore + worker task architecture recommended in VxWorks.
Interrupt Service Routine #
The ISR performs only minimal work:
void pci9030isr(void) {
if (is_our_interrupt()) {
clear_interrupt();
semGive(intSem);
}
}
Dedicated Interrupt Handling Task #
void pci9030inthandle(void) {
while(1) {
semTake(intSem, WAIT_FOREVER);
process_data();
}
}
Why This Design Matters #
This architecture provides:
- Minimal ISR latency
- Deterministic interrupt response
- Reduced interrupt lock time
- Better system scalability
- Safer synchronization
It is considered best practice for VxWorks real-time drivers.
๐ฆ Communication Protocol Design #
Data is transferred using fixed-length 16-byte packets.
Packet Structure #
| Field | Size |
|---|---|
| Data Count | 1 byte |
| Identifier | 3 bytes |
| Data Payload | Up to 10 bytes |
| Checksum | 1 byte |
Identifier Examples #
| Identifier | Function |
|---|---|
GJR |
Fiber read |
GWJ |
Fiber write |
GWA~GWD |
Digital outputs |
Checksum Mechanism #
The checksum is generated using the low byte of the cumulative sum of all preceding bytes.
Advantages:
- Simple implementation
- Fast DSP calculation
- Minimal overhead
- Adequate for controlled optical links
๐ System Performance and Validation #
Testing confirmed:
- Reliable high-speed data transmission
- Stable PCI bus operation
- Correct interrupt handling
- Deterministic DSP communication
- Strong EMI resistance
- Improved navigation communication accuracy
Measured Benefits Over RS422 #
| Feature | RS422 | Fiber Design |
|---|---|---|
| Bandwidth | Low | High |
| EMI Immunity | Moderate | Excellent |
| Isolation | Limited | Complete |
| Scalability | Limited | Excellent |
| Latency | Higher | Lower |
The optical solution significantly improved overall system robustness.
๐ก Reliability and Real-Time Considerations #
Several design choices enhance reliability:
Hardware #
- Optical isolation
- FIFO buffering
- CPLD deterministic timing
- Dual-port RAM synchronization
- CPCI industrial backplane
Software #
- VxWorks deterministic scheduler
- Deferred interrupt handling
- Binary semaphore synchronization
- Dedicated processing tasks
- Modular driver architecture
Together, these provide a highly reliable embedded communication platform.
๐ฎ Modern Perspective (2026) #
While the original architecture remains technically sound, modern embedded systems would likely adopt newer technologies.
Modern Hardware Alternatives #
- PCIe instead of CPCI PCI
- FPGA-integrated PCIe endpoints
- 10G/25G optical Ethernet
- RapidIO or Aurora serial links
- TSN-enabled deterministic Ethernet
Modern Software Enhancements #
- VxWorks 7 / Helix SMP support
- Real-Time Processes (RTPs)
- Driver Framework integration
- Device Tree-style hardware configuration
- Improved tracing and observability
Modern Aerospace Networking #
Contemporary avionics and navigation systems increasingly combine:
- Fiber optics
- TSN (Time-Sensitive Networking)
- ARINC 664 / AFDX
- Deterministic Ethernet
- Redundant switched fabrics
These technologies provide higher bandwidth, fault tolerance, and synchronization precision.
โ Conclusion #
The CPCI fiber optic communication card based on the PCI9030 bridge and VxWorks successfully addresses the bandwidth and reliability limitations of traditional RS422 communication in inertial navigation systems.
Key achievements include:
- High-speed 155 Mbps optical communication
- Deterministic VxWorks device driver architecture
- Efficient DSP-host communication via dual-port RAM
- Excellent anti-interference capability
- Scalable and maintainable embedded design
The combination of fiber optics, CPCI architecture, DSP processing, and VxWorks real-time software provides a powerful communication platform suitable for aerospace, industrial control, and mission-critical embedded applications.
References #
- VxWorks Device Driver Developerโs Guide
- PLX PCI9030 Data Sheet and Programmer Manual
- Cypress CY7B923/CY7B933 Documentation
- TMS320F2812 Technical Reference Manual
- CompactPCI Specification Documentation
- ANSI X3.230 8B/10B Encoding Standard
Reference: VxWorks CPCI Fiber Communication Card Design and Driver Development