ARM and VxWorks-Based Microcomputer Excitation Regulator

ARM and VxWorks-Based Microcomputer Excitation Regulator

⚙️ Abstract

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Traditional generator excitation regulators built on 16-bit processors and foreground/background software architectures face growing limitations in computational capability, scalability, reliability, and networking support. As excitation control algorithms become more advanced, legacy platforms struggle to satisfy modern real-time and functional requirements.

This article presents a new microcomputer excitation regulator architecture based on the 32-bit AT91RM9200 processor featuring the ARM920T core and the VxWorks real-time operating system. The design integrates a CPLD-based phase-shifted triggering subsystem to ensure highly reliable thyristor pulse generation and eliminate excitation-loss risks caused by software failures.

The platform also incorporates high-speed Ethernet communication for networked control and industrial integration. Combined with a modular VxWorks software architecture and comprehensive anti-interference strategies, the system significantly improves real-time responsiveness, reliability, maintainability, and extensibility compared with conventional excitation regulators.

🔌 Limitations of Traditional Excitation Regulators

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Since the 1980s, microcomputer-based excitation regulators have been widely deployed in power generation systems. Most conventional solutions are based on 16-bit processors such as Intel 80C196 or TI DSP2407 and rely on foreground/background software architectures.

Although these systems achieved acceptable performance in earlier deployments, several architectural limitations have become increasingly apparent.

Insufficient Computing Performance

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Modern excitation control increasingly depends on advanced algorithms such as:

• Fuzzy control
• Nonlinear optimal control
• Adaptive control
• Robust control strategies

These computationally intensive algorithms exceed the practical performance limits of traditional 16-bit processors, particularly under strict real-time constraints.

Limited Reliability and Expandability

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Conventional trigger and sampling circuits often depend on CPU timers and external comparator logic, introducing several reliability concerns:

• Vulnerability to software runaway
• Reduced fault tolerance
• Limited communication capability
• Difficult integration with distributed control systems (DCS)

In addition, older architectures typically lack standardized high-speed networking interfaces.

Increasing Software Complexity

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As functionality expands, traditional foreground/background software models become difficult to maintain and scale. Common issues include:

• Poor modularity
• Complex interrupt coordination
• Reduced portability
• Difficult debugging and maintenance

To address these challenges, a new excitation regulator platform based on ARM9 and VxWorks was developed.

🖥️ Hardware Architecture

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The hardware platform consists of multiple functional modules:

• AC/DC signal processing
• Analog-to-digital conversion
• RM9200 + CPLD control subsystem
• Memory interface
• Synchronization voltage shaping
• Phase-shifted trigger generation
• Digital I/O
• Human-machine interface
• Ethernet communication
• Power management

The architecture emphasizes deterministic real-time control, hardware reliability, and system scalability.

AT91RM9200 ARM Processor

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The controller core uses the AT91RM9200 industrial-grade ARM9 processor based on the ARM920T architecture.

Key features include:

• Up to 200 MIPS processing performance
• 60 MHz peripheral bus
• Instruction and data cache
• DMA support
• 122 multiplexed I/O pins
• 32 interrupt sources
• 6 timers
• 5 serial communication interfaces
• Integrated 10/100 Mbps Ethernet MAC
• USB 2.0, SPI, and TWI support

Compared with legacy 16-bit solutions, the ARM9 platform significantly improves:

• Real-time processing capability
• Peripheral integration
• System reliability
• Communication performance
• Future scalability

The high integration level also simplifies peripheral circuit design and reduces hardware complexity.

🔁 CPLD-Based Phase-Shifted Trigger Design

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Traditional excitation trigger circuits often rely directly on CPU timers and comparators. Under abnormal software conditions such as program crashes or watchdog resets, trigger generation may fail, potentially causing generator excitation loss.

To eliminate this risk, the new design introduces an XC95144 CPLD-based trigger subsystem.

CPLD Trigger Advantages

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The CPLD interfaces with the RM9200 through a 16-bit data bus operating at up to 60 MHz. The processor calculates the firing angle and transfers it to the CPLD, which independently performs:

• Frequency measurement
• Phase-shift computation
• Six-pulse thyristor trigger generation

The trigger subsystem supports:

• Phase-shift range from 0° to 180°
• Theoretical resolution of approximately 0.0027°

Most importantly, pulse generation remains operational even if the main CPU software becomes unstable. This hardware-level independence dramatically improves excitation reliability and system safety.

Reliability Improvements

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The CPLD-based approach offers several practical benefits:

• Reduced CPU timing overhead
• Deterministic pulse generation
• Improved electromagnetic immunity
• Elimination of trigger jitter caused by software scheduling
• Prevention of excitation loss during processor faults

This architecture is particularly valuable in high-power synchronous generator applications where excitation continuity is critical.

📡 High-Speed Data Acquisition System

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The excitation regulator supports 16 analog acquisition channels designed for synchronized high-speed sampling.

ADC Architecture

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The acquisition subsystem uses:

• MAX291 active filters for front-end signal conditioning
• Four AD7865 14-bit ADCs
• Simultaneous sampling across all 16 channels

Each AD7865 integrates four sample-and-hold circuits, eliminating the need for additional external multiplexers or sampling hardware.

Key performance metrics include:

• Total conversion time: approximately 10 μs
• Sampling rate: 1800 Hz
• 36 sampling points per power-frequency cycle

Interrupt-Driven Sampling

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The RM9200 timer subsystem generates synchronized PWM trigger signals and captures system frequency information.

After conversion completes:

1. ADC completion signals are combined through the CPLD
2. The CPLD asserts external interrupt IRQ0
3. The ARM processor services the acquisition interrupt

This approach minimizes CPU overhead while maintaining deterministic sampling timing and high acquisition precision.

🌐 Ethernet Communication Architecture

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Modern excitation systems increasingly require networked monitoring and remote integration with plant automation infrastructure.

To satisfy these requirements, the design uses the RM9200 integrated Ethernet MAC controller with:

• DMA support
• FIFO buffering
• 10/100 Mbps Ethernet capability

Compared with traditional fieldbus communication methods, Ethernet provides:

• Higher bandwidth
• Standardized networking
• Easier integration with DCS platforms
• Improved scalability
• Lower communication latency

The architecture enables reliable real-time communication between the excitation regulator, supervisory control systems, and industrial monitoring platforms.

🧠 VxWorks-Based Software Architecture

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Why VxWorks?

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As embedded excitation control systems grow more complex, traditional foreground/background software models become increasingly difficult to maintain.

VxWorks was selected due to several advantages:

• Deterministic real-time scheduling
• High system reliability
• Compact kernel footprint
• Rich synchronization primitives
• Mature networking stack
• Excellent modularity and portability

The operating system supports:

• 256-level priority-based preemptive scheduling
• Sub-millisecond response latency
• Minimal kernel footprint of approximately 8 KB

These characteristics make VxWorks highly suitable for industrial real-time control systems.

🧵 Interrupt and Task Partitioning

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The software architecture divides functionality into dedicated interrupts and tasks following real-time scheduling principles.

Interrupt Subsystem

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The design includes four high-priority interrupt sources:

1. A/D conversion interrupt
2. Sampling frequency capture interrupt
3. Host computer communication interrupt
4. DCS communication interrupt

Interrupt service routines (ISRs) remain intentionally lightweight and primarily perform:

• Fast data acquisition
• Event acknowledgement
• Semaphore posting

The intConnect() interface is used to register interrupt handlers.

Task Scheduling Structure

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The system defines seven major tasks ordered by execution priority:

1. Control law computation
2. Limit checking
3. Fault detection
4. Host data upload
5. DCS data upload
6. Human-machine interaction
7. Fault recording

The highest-priority control task executes PID and Power System Stabilizer (PSS) algorithms.

During critical calculations, the scheduler is temporarily locked using taskLock() to prevent unwanted task switching and ensure deterministic execution timing.

Inter-Task Communication

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The system uses multiple VxWorks synchronization mechanisms:

• Semaphores
• Mutexes
• Message queues
• Shared memory

Mutex protection is specifically applied to prevent priority inversion problems in shared resources.

This modular task-based architecture significantly improves:

• Software maintainability
• Scalability
• Debugging efficiency
• Fault isolation

🛡️ Anti-Interference Design

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Generator excitation regulators operate in environments with strong electromagnetic interference. Both hardware and software protection mechanisms are therefore essential.

Hardware Protection Measures

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The hardware design incorporates:

• Optical isolation for communication interfaces
• Transformer isolation
• Isolated DC/DC power supplies
• Buffer drivers for pulse outputs
• Separate analog and digital grounding
• Multi-layer PCB routing
• Enhanced capacitor filtering

Single-point grounding is implemented at the A/D subsystem to reduce ground-loop interference.

Software Reliability Measures

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Software-level protection includes:

• Digital filtering of sampled signals
• Watchdog monitoring through VxWorks
• Fault recovery mechanisms
• Robust task synchronization

These combined measures substantially improve long-term operational stability in industrial power environments.

📈 System Benefits and Engineering Value

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Compared with traditional 16-bit excitation regulators, the ARM9 and VxWorks-based architecture delivers major improvements across multiple dimensions.

Core Advantages

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The new platform provides:

• Higher computational performance
• Improved real-time responsiveness
• Better electromagnetic robustness
• Reliable trigger generation
• High-speed Ethernet networking
• Simplified software maintenance
• Stronger system scalability

The CPLD trigger subsystem is especially important because it guarantees excitation continuity even during CPU instability.

Practical Deployment Potential

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Prototype testing demonstrates that the regulator is suitable for medium and large synchronous generator applications requiring:

• High reliability
• Networked supervision
• Advanced control algorithms
• Industrial-grade real-time performance

The architecture also establishes a strong foundation for future integration of:

• Nonlinear robust control
• Intelligent excitation algorithms
• Fuzzy control
• Adaptive regulation techniques

🏁 Conclusion

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The ARM and VxWorks-based microcomputer excitation regulator represents a significant advancement over traditional 16-bit excitation control systems.

By combining:

• The AT91RM9200 ARM9 processor
• VxWorks real-time operating system
• CPLD-based trigger logic
• High-speed Ethernet communication

the design achieves substantial gains in reliability, deterministic control, software maintainability, and industrial scalability.

The modular hardware/software architecture not only improves present-day excitation performance but also provides a future-ready platform for next-generation intelligent generator control systems.